@ESP_igrr Thank you for the clarification. Your support is excellent. However I must admit I was hoping there would be a solution. The fact that the clock frequency for the CAN controller cannot be reduced does put some limits on the usage scenarios for the ESP32 CAN. Without being able to reduce th...

@ESP_igrr: I thought that would be the case. Thank you for clarification. I was hoping to be able to reduce the APB_CLK so the CAN controller can run on a lower clock frequency so we can support certain standard baudrates. Seems I have run out of options now (refer to https://www.esp32.com/viewtopic...

Following conversation above, does the Wifi and BT subsystems depend on APB clock to be 80MHz or can APB clock be changed to a different value without affecting Wifi & BT?

@rudi: Thank you for your replies. I am aware that the CAN controller is a SJA1000 and I have worked with the SJA1000 before, so know the chip quite well. I also have access to the ESP32 Technical Reference. But the ESP32 offers little information about the possible clock sources of the CAN controll...

This also can be verified using a CAN bit rate calculator like this one:

https://www.kvaser.com/support/calculat ... alculator/

In order to achieve a 10kbps CAN bitrate, the clock speed for the CAN controller must not be higher than 32 MHz. The CAN controller is not documented much, so I am hoping that there is a register to either pre-scale the clock or a clock divider of some sort or to use a different and slower clock sou...

@rudi: Its not a matter of software but hardware capabilities of the ESP32 chip. The baud rate prescaler in the SJA1000 is only 6 bit wide, resulting in a max pre-scaler value of 64. As a result the longest time quanta achievable is 1.6us. The max number of time quanta we can use with a SJA1000 is 2...

Hi all, The ESP32 CAN controller is clocked with APB clock of 80 MHz. Using this clock it won't be possible to operate with the CANopen standard bit rates of 5kbit/s, 10kbit/s and 20kbit/s. Higher bit rates are no problem, all standard bitrates from 50kbit/s upwards work. Is there a possibility to u...

@ aaquilina Are you using my PR? If yes, it has a small bug which I have not fixed yet in the PR which may cause this issue: Try changing uart_set_rs485_hd_mode to esp_err_t uart_set_rs485_hd_mode(uart_port_t uart_num, bool enable) { UART_CHECK((uart_num < UART_NUM_MAX), "uart_num error", ESP_FAIL);...

@aaquilina: Of course it has to enabled as well. Before the FIFO is written to you have to set the GPIO and also enable the interrupt. There are two locations in uart.c where this needs to be done. Once in uart_fill_fifo and once in the ISR. I submitted a PR with my code, so you can check it out. Pl...