Search found 92 matches
- Tue Jul 17, 2018 5:52 pm
- Forum: Hardware
- Topic: SPI WP signal
- Replies: 2
- Views: 5276
Re: SPI WP signal
Even with flash write status register command (flash_wrsr) WP signal does not change
- Sat Jul 14, 2018 8:54 am
- Forum: Hardware
- Topic: SPI WP signal
- Replies: 2
- Views: 5276
SPI WP signal
Hi, from ESP32 Technical Reference Manual: SPI_WP This bit determines the write-protection signal output when SPI is idle. 1: output high; 0: output low. (R/W) Modifying this bit changes output level of WP pin but it is kept all the time high / low - it does not change during SPI transmission. Tried...
- Sat Jul 14, 2018 8:38 am
- Forum: General Discussion
- Topic: GPIO Interrupt Latency - once more
- Replies: 5
- Views: 8770
Re: GPIO Interrupt Latency - once more
Hello mTron47, from my experience I can only recommend you using higher level interrupts in assembly. What would you like to do in an interrupt routine? If you need to set some pins high / low in reaction to a gpio input you can probably take a look at hardware peripherals - MCPWM capture mode maybe?
- Wed Jul 11, 2018 7:13 pm
- Forum: General Discussion
- Topic: Detect if new software flashed
- Replies: 5
- Views: 6004
Re: Detect if new software flashed
In fact there probably is SHA256 checksum of ESP image in flash so you don't have to compute it. Take a look at https://github.com/espressif/esp-idf/blob/master/components/bootloader_support/src/esp_image_format.c . Unfortunately there is no note about it here https://github.com/espressif/esptool/wi...
- Mon Jul 09, 2018 12:42 pm
- Forum: ESP-IDF
- Topic: Critical Code section
- Replies: 4
- Views: 20161
Re: Critical Code section
uint32_t volatile register ilevel = XTOS_DISABLE_ALL_INTERRUPTS; //critical section XTOS_RESTORE_INTLEVEL(ilevel); from xtruntime.h This critical section disable mutual cpu acess? I need to prevent both core to acess same "line in code" with more fast way possible... (Without method of freertos lik...
- Sun Jul 08, 2018 5:13 pm
- Forum: General Discussion
- Topic: Does enabling the pulse counter turn on the GPIO pull-up?
- Replies: 6
- Views: 9209
Re: Does enabling the pulse counter turn on the GPIO pull-up?
Perhaps this should be a configuration option? I'm now running on a non-standard kernel - I can't be the only person that will get caught out by this, surely? In my opinion ESP-IDF comes with too many assumptions (like this one). I am making lower level SDK but it is still in an early beggining. Fr...
- Sun Jul 08, 2018 2:53 pm
- Forum: General Discussion
- Topic: Does enabling the pulse counter turn on the GPIO pull-up?
- Replies: 6
- Views: 9209
Re: Does enabling the pulse counter turn on the GPIO pull-up?
Are you using ESP-IDF? If so then look at this line https://github.com/espressif/esp-idf/blob/a3c43251b4b37bc3ec105a10f2e1413b14420da3/components/driver/pcnt.c#L117 . You can change gpio_set_pull_mode(pulse_io, GPIO_PULLUP_ONLY); to gpio_set_pull_mode(pulse_io, GPIO_FLOATING); and see if it helps.
- Fri Jul 06, 2018 7:52 am
- Forum: General Discussion
- Topic: What would you like to see in The Next Chip?
- Replies: 426
- Views: 785741
Re: What would you like to see in The Next Chip?
Please be sure to fix SPI CS pre-transmission delay for full duplex mode (and other modes) in the next chip. It is such a shame that it works only in half duplex now. Generally speaking CS should be enabled before clock signal
- Wed Jul 04, 2018 11:42 am
- Forum: General Discussion
- Topic: Internal 8 MHz clock as CPU source
- Replies: 0
- Views: 2224
Internal 8 MHz clock as CPU source
I am trying to use internal 8 MHz clock as source for CPU. I know that ESP-IDF does not support this option so I used technical reference manual. Steps performed: extern uint32_t g_ticks_per_us_pro; g_ticks_per_us_pro = 40; RTC.clk_conf.enb_ck8m = 0; RTC.timer1.ck8m_wait = 1; RTC.clk_conf.ck8m_dfreq...
- Sun Jul 01, 2018 11:39 am
- Forum: General Discussion
- Topic: [esptool] segments with load 0x00000000
- Replies: 11
- Views: 12093
Re: [esptool] segments with load 0x00000000
I think I understand that segments in flash need to be 64K aligned so that they can be mapped by the MMU component. For example, I may have: [Segment A: 10K] [Padding: 54K] [Segment B: 20K] [Padding: 44K] [Segment C: 30K] This seems to result in an image bin file size of about 158K. However, if we ...