CP2102N and ESP32

[esp_enthousiast]

Hello,

Having studied the (reference) designs of the CP2102N based ESP32-devkits boards.
(with the transistors used for DTR, EN, RTS and IO0.)

ESP32_DEVKITS_20190621.pdf
was one of my sources, but a multiple of others share the same idea.
(or just copied and pasted it)

I'm confused as to how this actually works.

Code: Select all

ESP32 autoprogram:

DTR | RTS -> EN | IO0
  1    1        1     1
  0    0        1     1
  1    0        0     1
  0    1        1     0

In what order are these signals raised and lowered, so that the ESP32 "knows" it is in "program mode"?

Thankyou, for any enlightenment.

[ESP_Sprite]

Generally, the ESP32 switches to download mode when the IO0 signal is low when EN goes from low to high. Do keep in mind that there's a RC network on EN, so if EN is released, it takes a fraction of a second to actually go high.

[esp_enthousiast]

Hello ESP_Sprite, thank you for taking the time to answer my question.

However, I am still confused.
Maybe because I was too concise?
Then I will try to be more verbose this time.

In our project I am using an ESP32-wrover-e module that I would like to program over USB-C(2.0) from any computer able to run "esptool.py".

I came across the devkits that use a CP2021n, and thought I might implement that.

I have read the datasheets, studied the schematics, and they (almost) confirm your answer:
- "Bootmode is enabled when IO0 is held low after EN goes high."

I understand that.

I also noticed that the CHIP_PU-pin of the ESP32-D0WD chip itself, is directly connected to the EN pin on the module.

The datasheets advise to hold EN low after power-up with an RC-network.


In the schematic I quoted earlier the values used are: 10k and 100n, to delay EN.

But there are also capacitors over the buttons: SW1 and SW2. (wired to IO0 and EN respectively)

Yielding the total capacity over the EN pin to be 200n, and over the IO0 pin 100n.
timing values would be:
pin | RCtime
EN | 10e3 x 200e-9 = 2ms
IO0 | Rpullup x 100e-9 = ? ms

Which would yield an uncertainty in the state of IO0, since its Rpullup can differ from chip to chip.

Some devboards might never go beyond boot mode, if the internal pullup was to weak?

::

That said, lets return to my actual question:

"What I fail to understand -and what is not mentioned in the cp2102n documentation either- is the order in which the signals are asserted, and what sequence of DTR and RTS makes the ESP32 module enter bootmode."

I realise this looks like a cp2102N related question, yet I still hope to find an answer in this forum.
(If only because the devkits are made by espressif also, so they should know.)

Best regards, &c.

[ESP_Sprite]

IO0 does not and should not have a capacitor on devboards. In ESP32_DEVKITS_20190621.pdf, that capacitor is marked as NC meaning there is a footprint for it on the PCB but it's not placed. Some people read over that and copy the capacitor, and the effect is that the chip will always boot up in download mode when powered on, aside from possibly never getting out of that as you correctly inferred.

DTR and RTS are pulled from software, e.g. by esptool.py. I'm not sure if the order is actually documented anywhere else beyond the source code for that tool, as there's a few different strategies that are used to also make other auto-reset configurations work.

[esp_enthousiast]

Hello ESP_Sprite,

Thank you for pointing out that 'C14' (in the aforementioned schematic) should be read as: "Don't place".
(I probably missed that because I was unfamiliar with the usage of "NC" for "NOSTUFF", teaches me to be more observant.)

It would seem I indeed have to "jump in the rabbit hole". i.e. Read the source code of esptool.py, before I really understand how the mechanism works.
As I understand it now (with unpopulated C14) race-conditions might still occur.

Oh well, if that's how it is: than that's how it is.

It only means more work for me, which I would have liked to invest elsewhere.

It might have been nice to have had this already documented and answered.
Yet maybe my findings might reach the documentation, and so prevent others from having to do this work.

[ESP_Sprite]

I don't understand why specifically you need to know the details on how esptool.py does this? If you need to write your own code to program an ESP32 using the CP2102, you just implement something that works given the hardware.

[username]

@esp_enthousiast, there is a document (don't remember which one) that examples the timing parameters for EN & GPIO0.
IMHO, if your not designing your own programmer board & software, make the move to the ESP-S3, and eliminate all the extra hardware, and just use built in USB interface to flash it.