ESP32-S3 - I2S during Light Sleep

timstercb
Posts: 3
Joined: Sun Dec 10, 2023 5:38 pm

ESP32-S3 - I2S during Light Sleep

Postby timstercb » Thu Feb 08, 2024 2:06 am

Hi,

I have an application where I am recording from stereo PDM microphones for a short duration (~10sec) then storing this on an SD card, along with values from some environmental sensors.

Everything is working nicely, but I'd like to improve the power performance for instances where the device is running on battery power.

Most of the time in the app is spent waiting on the blocking i2s_channel_read function to return when the data is available in the DMA buffer. I'd love to use light sleep if it's an option.

I've read through the datasheets, but for the life of me can't tell whether both the I2S and DMA peripherals will remain active during light sleep, and if so, how to properly configure them so that they aren't clock gated.

Any insight would be greatly appreciated!

Thanks!
-Tim

liaifat85
Posts: 139
Joined: Wed Dec 06, 2023 2:46 pm

Re: ESP32-S3 - I2S during Light Sleep

Postby liaifat85 » Thu Feb 08, 2024 10:24 am

you can buffer incoming data in RAM before entering sleep mode and then process it after waking up.

timstercb
Posts: 3
Joined: Sun Dec 10, 2023 5:38 pm

Re: ESP32-S3 - I2S during Light Sleep

Postby timstercb » Fri Feb 09, 2024 1:37 am

Unfortunately, that won't save any power, as what I'm wanting is to sleep during the 9sec PDM recording to DMA, when the processor is doing nothing.

MicroController
Posts: 1221
Joined: Mon Oct 17, 2022 7:38 pm
Location: Europe, Germany

Re: ESP32-S3 - I2S during Light Sleep

Postby MicroController » Tue Feb 13, 2024 10:35 am

There may be some combination of clock gating/'force PU' settings which could work, stopping only the CPU but nothing else. Light sleep however, among other things, clock-gates and powers down the internal RAM ("retention mode"), so DMA cannot work.

Probably the best you can do is to switch the CPU clock down to 80MHz while waiting for the I2S transfer.
I imagine that the CPU core alone, just waiting for an interrupt, doesn't contribute too much to the power consumption while RAM and much of the high-speed clocks (APB,...) are running anyway. (Anecdotally, on other µC's I found that the PLL would contribute significantly to the idle power (like, 100MHz/2 needing more power than 50MHz/1), which seems plausible for the S3 too when the PLL is ticking along at 480MHz with not much else going on.) With CPU_CLK at 80MHz, the PLL can run at 'only' 320MHz; better yet would be to run without the PLL, i.e. CPU_CLK = XTAL_CLK = 40MHz, which you could also try.

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