One use case for me is the LP CPU checking sensor data with some basic processing while the main CPU is in deep sleep mode. In a battery driven system the main CPU would only be started when it comes to enhanced processing or wireless communication.
I use ESP-IDF v5.2-beta1-263 because the C6 support is under progress.
Some questions regarding the LP CPU:
- Will there be ADC access possible from the LP CPU? Table 7-5 in the Technical Reference Manual mentions this. So is only the API missing? In the "ESP32-C6 support status" (https://github.com/espressif/esp-idf/issues/10423) for ESP-IDF v5.1 no LP feature is mentioned.
- The C6 LP CPU is a RISC-V CPU, but it looks different to the ULP-RISC-V CPU used in S2 and S3 (RV32IMAC ISA (instruction set architecture) vs. RV32IMC). Also the API is different. In the announced P6 the LP CPU looks similar, but with 40 MHz and more LP modules like PMU and SPI. Is that correct?
- Is there any way of checking the actual LP SRAM usage? There are only 16 KB available.