Full duplex SPI MODE 3 CS line pulls down at same time of CLK

dzRBRglobal
Posts: 11
Joined: Thu Jul 26, 2018 3:20 pm

Full duplex SPI MODE 3 CS line pulls down at same time of CLK

Postby dzRBRglobal » Wed Sep 26, 2018 6:27 pm

When capture signal on my digital analyzer in mode 3, the digital analyzer always complains "CLK idle error". If I set my digital analyzer to mode 0, it can decode the signal. I found the CS pulls down at same time of CLK. Should the CS pull down before CLK?
Attachments
DECODE at mode 3.png
DECODE at mode 3.png (30.72 KiB) Viewed 4102 times
cs and clock at same time.png
cs and clock at same time.png (37.64 KiB) Viewed 4102 times

michprev
Posts: 92
Joined: Fri Aug 04, 2017 8:57 pm

Re: Full duplex SPI MODE 3 CS line pulls down at same time of CLK

Postby michprev » Wed Sep 26, 2018 7:05 pm

Generally CS should be always toggled before CLK signal. There is a hardware bug where setting cs_ena_pretrans does not have any effect in full duplex.

You can control CS line as GPIO (set it low before SPI transmission, set it high after transmission).

dzRBRglobal
Posts: 11
Joined: Thu Jul 26, 2018 3:20 pm

Re: Full duplex SPI MODE 3 CS line pulls down at same time of CLK

Postby dzRBRglobal » Mon Oct 01, 2018 1:24 pm

Thank you very much for your reply.
So what is the work around for now if I want to use DMA ? define a GPIO and set it in pre call function and reset in post call function?

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