Re: Transparent Wi-Fi module with RMII input
Posted: Mon Feb 27, 2017 7:34 am
hi
Are there progresses?
best wishes
rudi
Are there progresses?
best wishes
rudi
ah.. you have a working model? fine!ESP_Sprite wrote:.. that we can sell.
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT)
PoE very welcome -ESP_Sprite wrote:..The reference design includes PoE as well,....I'll see if I can post the schematics.
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extern void rtc_plla_ena(bool ena, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
// for rev0 chip: f_out = f_xtal * (sdm2 + 4) / (2 * (o_div + 2))
// so for 40MHz XTAL, sdm2 = 1 and o_div = 1 will give 50MHz output
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_H_DIV_NUM, 0);
REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_DIV_NUM, 0);
REG_CLR_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_INT_OSC_EN);
rtc_plla_ena(1, 0, 0, 1, 0);
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rtc_plla_ena(1, 0, 0, 0, 0);
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rtc_plla_ena(1, 0, 0, 1, 0);
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rtc_plla_ena(1, 0, 0, 2, 0);
and rtc_plla_ena is not described at time
rtc_clk.o rtc_xtal_32k_ena
rtc_clk.o rtc_8m_ena
rtc_clk.o rtc_plla_ena
rtc_clk.o rtc_set_slow_freq
rtc_clk.o rtc_set_fast_freq
rtc_clk.o rtc_bbpll_md
rtc_clk.o rtc_init_xtal_freq
rtc_clk.o rtc_get_xtal
rtc_clk.o rtc_apb_freq_up
rtc_clk.o rtc_uart_div_modify
rtc_clk.o rtc_uart_tx_wait_idle
rtc_clk.o rtc_set_cpu_freq
rtc_clk.o rtc_init_clk
rtc_clk.o rtc_init_clk_lite
What is the correction?rudi ;-) wrote:
btw, there a small parameter idx mistake in the given pvParameter
but have figured it out