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Board1 has adc 2-point cal with 3/4 coding
Board 2 has adc vref with no coding
There's no technical reason for this. The two changes are unrelated apart from the fact they were applied at the same time, and have been removed at the same time.WiFive wrote: why does BLK3_PART_RESERVE auto select 3/4?
The hardware algorithm is always AES-256. With 3/4 coding scheme, the key is extended (bits 64-127 are repeated) in order to make a 256 bit key. Full details are in the change which is currently being reviewed.WiFive wrote:How does the encryption engine handle the 192bit key?
Currently all modules with 2 point calibration have BLK3_PART_RESERVE=1 and CODING_SCHEME=1 both set, yes.WiFive wrote:Will all 2 point Cal modules ship with this configuration?
As mentioned above, there'll be a statement on this soon.WiFive wrote:Is this an isolated batch and what are the dates/Mac ranges? how can we know when buying from a distributor what config we are getting (vref vs 2 pt)?
Well the TRM saysESP_Angus wrote:There's no technical reason for this. The two changes are unrelated apart from the fact they were applied at the same time, and have been removed at the same time.WiFive wrote: why does BLK3_PART_RESERVE auto select 3/4?
So is this a hardware bug or a design choice?When the value of BLK3_part_reserve is 0, coding_scheme, BLOCK1, BLOCK2, and BLOCK3 can be set to any
value.
When the value of BLK3_part_reserve is 1, coding_schemeBLOCK1BLOCK2 and BLOCK3 are controlled by
3/4 coding scheme
I see. This is a design choice that's been written into the TRM. I don't think there's any technical reason why there couldn't be a chip with BLK3_PART_RESERVE=1 and CODING_SCHEME=0, but no such device is produced (or planned).WiFive wrote: Well the TRM saysSo is this a hardware bug or a design choice?When the value of BLK3_part_reserve is 0, coding_scheme, BLOCK1, BLOCK2, and BLOCK3 can be set to any
value.
When the value of BLK3_part_reserve is 1, coding_schemeBLOCK1BLOCK2 and BLOCK3 are controlled by
3/4 coding scheme
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